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sa2400a single chip transceiver for 2.45 ghz ism band product data 2002 nov 04 integrated circuits
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2 2002 nov 04 853-2320 28727 1. description the sa2400a is a fully integrated single ic rf transceiver designed for 2.45 ghz wireless lan (wlan) applications. it is a direct conversion radio architecture that is fabricated on an advanced 30 ghz f t bicmos process. the sa2400a combines a receiver, transmitter, and lo generation into a single ic. the receiver consists of a low-noise amplifier, down-conversion mixers, fully integrated channel filters, and an automatic gain control (agc) with an on-chip closed loop. the transmitter contains power ramping, filters, up-conversion, and pre-drivers. the lo generation is formed by an entirely on-chip vco and a fractional-n synthesizer. typical system performance parameters for the receiver are 93 db gain, 7.5 db noise figure, input-referred third-order intercept point (iip3) of +1 dbm, agc settling time of 8 m s, and tx-to-rx switching time of 3 m s. the transmitter typical system performance parameters are an output power range from 7 dbm to +8 dbm in 1 db steps, 40 dbc carrier leakage after calibration, 22 db sideband suppression, in-band common mode rejection of 30 db, and rx-to-tx switching time of 3 m s. 2. functional blocks and features the block diagram of the sa2400a direct conversion transceiver is given in figure 1. it consists of the following functional blocks: ? a 79 db adjustable gain range direct conversion zero if receiver with 3 m s (typical) tx to rx switching time, and comprising the following: front-end lna with two internal gain states a fast on-chip closed loop composite rf and if agc with zoomed analog rssi output and 8 m s settling time quadrature downconverters from 2.45 ghz rf directly to zero if on-chip fast baseband dc cancellation with automatically stepped bandwidths of 10 mhz, 1 mhz, 100 khz, and 10 khz, settling within 813 m s for a dc error of 10% that decays to 1%. fully integrated channel filters, appropriate for 11 msymbols/s qpsk modulation rf bandwidth. ? an i/q upconverter from baseband directly to 2.45 ghz, with +8 dbm output power, 40 dbc typical carrier leakage (calibrated) and 3 m s (typical) rx to tx switching time, and comprising the following: wide band iq modulator producing better than 14% evm for 11 msymbols/s qpsk modulation integrated reconstruction and spectral shaping filters at i and q modulation input that is driven by an external d/a. high common mode rejection to input ground bounce. fir-dacs for digital i/q input feeding the analog signal path and including additional filtering for spectral shaping. 2.45 ghz power amplifier driver with +8 dbm maximum output, 15 db adjustable gain in 1 db steps and a second switched output at 1.5 dbm power level with similar gain adjustments that are set by a separate register. completely on-chip calibration for carrier leakage compensation. internal power ramping with 2 m s delay and 0.5 m s ramp-up time. ? a fractional-n frequency synthesizer with on-chip vco and xo ? a 3-wire bus for control of most blocks ? an additional high speed 3-wire bus for full control of rx-gain and dc-offset compensation parameters with 44mbits/s. ? fast tx-rx switching based on a single digital input pin. ? reference currents and voltage for supply of baseband processor and pa-chip. 3. applications ? ieee 802.11 and 802.11b radios supports dsss and cck modulation supports data rates: 1, 2, 5.5, and 11 mbps ? 2.45 ghz ism band wireless communication devices table 1. ordering information type number package type number name description version SA2400ABE lqfp48 plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 3 4. block diagram agc state machine 2 rf_in 2 rssi a/d 2 rx_out_i rssi rx_out_q agcset agcreset 0 90 control sen sclk sdata txrx tx_hi filter tuning 0 90 tx_out_hi tx_out_lo 2 power detector a/d txcal state machine pll cp :2 d/a v_tune xtal d/a xo ref_clk 2 lock firdac firdac tx_in_i data_i data_q tx_in_q 2 2 sr02386 figure 1. sa2400a functional block diagram.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 4 5. pinning information sr02387 a_gnd tx_hi a_v tx_out_lo sa2400a dd a_gnd tx_out_hi_p tx_out_hi_m a_gnd sen sdata sclk tx/rx tx_in_i_p/ tx_data_i tx_in_i_m/ tx_data_q tx_in_q_p tx_in_q_m rx_out_q_p rx_out_q_m rx_out_i_p rx_out_i_m d_gnd ref_clk_out pll_gnd agcreset agcset idcout a_gnd gnd_lna rf_in_p rf_in_n gnd_lna test1 test2 v_2p5 a_v dd a_v dd rssi v_tune vco_v vco_p vco_m _pll cp lock xtal_1 xtal_2 d_v dd vco_gnd dd v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 figure 2. pin configuration.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 5 table 2. pin description pin type is designated by a = analog, d = digital, i = input, o = output symbol pin description type agcreset 1 agc start input di agcset 2 agc settled output do idcout 3 tx-mode: dc reference current ao a_gnd 4 analog ground gnd_lna 5 analog ground rf_in_p 6 rf input (positive) ai rf_in_n 7 rf input (negative) ai gnd_lna 8 analog ground a_v dd 9 analog supply test_1 10 test pin test_2 11 test pin v_2p5 12 dc reference voltage ao rssi 13 rssi output signal ao d_v dd 14 digital supply v_tune 15 vco tuning voltage ai vco_gnd 16 vco ground vco_v dd 17 vco supply vco_p 18 vco output/ external vco input ai/o vco_m 19 vco output/ external vco input ai/o v dd _pll 20 synthesizer supply cp 21 charge pump output ao lock 22 synthesizer lock indicator ao xtal_1 23 crystal input ai xtal_2 24 crystal input ai symbol pin description type pll_gnd 25 synthesizer ground ref_clk_out 26 reference clock output ao d_gnd 27 digital and analog ground rx_out_i_m 28 receive output ao rx_out_i_p 29 receive output ao rx_out_q_m 30 receive output ao rx_out_q_p 31 receive output ao a_v dd 32 analog supply tx_in_q_m 33 transmit input ai tx_in_q_p 34 transmit input ai tx_in_i_m/ tx_data_q 35 transmit input ai/di tx_in_i_p/ tx_data_i 36 transmit input ai/di tx/rx 37 tx/rx mode select di sclk 38 three-wire bus clock di sdata 39 three wire bus data di/o sen 40 three wire bus enable di a_gnd 41 analog ground tx_out_hi_m 42 transmit output, high power ao tx_out_hi_p 43 transmit output, high power ao a_gnd 44 analog ground tx_out_lo 45 transmit output, low power ao a_v dd 46 analog supply tx_hi 47 transmit output power level select di a_gnd 48 analog ground
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 6 6. functional description the sa2400a transceiver is intended for operation in the 2.45 ghz band, specifically for ieee 802.11b 1 and 2 mbits/s dsss, and 5.5 and 11 mbits/s cck standards. throughout this document, the operating rf frequency refers to the ism band between 2.4 ghz and 2.5 ghz. 6.1 rf vco the local oscillator is common to both the transmitter and the receiver. the rf vco is a differential 4.8 ghz oscillator with the frequency determining components internal to the ic. the vco is connected internally to a frequency divider and a quadrature generator circuit which produces the lo for the iq up- and downmixer. the divider output is also internally connected to the synthesizer, which can be programmed in order to produce steps of 0.5 mhz for the desired lo frequency. at the time of power-up, the vco must be calibrated by invoking the vcocalib mode by means of the three-wire bus. this operation will select an appropriate frequency band in the vco, thus compensating for process tolerances. the calibration takes up to 2.2 ms, after which the ic automatically enters the sleep mode. the synthesizer registers 0x00 through 0x03 must be re-programmed after completing the vcocalib. the 2.45 ghz lo can also be injected externally. 6.2 rf low noise amplifier the rf lna has differential inputs and an external balun is needed in the case of single-ended operation. it has two gain states which are controlled internally by the on-chip automatic gain control, or manually via the 3-wire bus. 6.3 downconversion mixers the rf signal is converted down directly to baseband by quadrature image-reject mixers. 6.4 receiver low-pass filter, baseband amplifiers the i and q low-pass filters are fully integrated chebychev active filters. the i and q pass band extends from dc to a 3 db corner at 7 mhz. additional adjustable gain is provided in baseband amplifiers to achieve a total adjustable gain range of 79 db. the rx output is provided in the form of differential i and q signals, which must be dc coupled to the adc inputs on a base band ic. 6.5 dc cancellation the rx chain also integrates a high-pass filter (dc notch) for cancellation of the dc offset inherent to zero-if operation. the high-pass filter has a programmable lower 3 db cutoff frequency of 10 mhz, 1 mhz, 100 khz or 10 khz. the dc offset cancellation occurs simultaneously with the agc settling process. during the agc settling phase (see below) the cutoff frequency is dynamically selected between 10 mhz and 1 mhz to quickly reduce dc offset values from +50 dbc to below 20 dbc relative to a 76 dbm antenna input signal before the rssi (see below) is internally sampled. after the agc settling, the high pass is configured for 100 khz for 5 m s before switching to a final 10 khz cutoff frequency. the low value of 10 khz is required for minimizing the signal distortion created by a high-pass function at zero frequency. the high-pass will then remain set to the 10 khz cutoff frequency until a new agc cycle is started. whenever there is a frequency change in the high-pass filter lower cutoff, the dc offset can change from a very low value to about 50% (1 mhz 100 khz step) or 10% (100 khz 10 khz step) of the signal level. this dc offset then decays according to the high-pass response of the filter. the cutoff frequency of the high-pass filter can also be selected manually by using the rxmgc mode. 6.6 agc the receiver contains a fully integrated automatic gain control loop. it works by adjusting the internal gain such that the rx output amplitude, as measured by the rssi (see below), meets a predefined target value. by default, the agc is always set to a default maximum gain (adjustable by register value gmax) whenever the sa2400a enters the receive mode of operation from another operational mode. it takes 5 m s for the receiver to settle when it enters this mode, which includes the time for dc offsets to be removed with a 1 mhz lower cut-off frequency of the high-pass filtering. this lower cut-off frequency of 1 mhz remains unchanged as long as the agc remains in the default maximum gain state. the agc must be invoked by providing a 0-to-1 transition on the agcreset pin, and keeping the signal on that pin to 1 for at least 5 m s. by successively reducing the gain from its initial maximum value, the loop searches for the correct gain value to provide a nominal output amplitude of 500 mv peak, differential for a qpsk signal (within 3 db dynamic error) at the output pins. this is achieved after a maximum of 8 m s. this time is defined by wait periods necessary to settle the receiver after gain switching actions. the individual wait periods can be adjusted by means of register settings. after completing the agc settling process, the agcset pin is set to 1 by the algorithm. the receiver gain then will not change again until another pulse is issued on the agcreset pin. for a subsequent agc operation, the receiver needs to enter its maximum gain state again. if another agcreset signal (as described above) is issued, the settling period will take an extra 3 m s, up to a total of 11 m s, since the first 3 m s will be spent on entering maximum gain mode and settling the receiver thereafter. to shorten this operation, the receiver can be forced to maximum gain (e.g., at a time when no signal is present) by issuing a 010 pulse of maximum 1 m s pulse width on the agcreset pin. the receiver will then enter maximum gain mode (the agcset signal will not be set to 1 after this), and a following 0-to-1 transition on the agcreset pin will start the settling sequence from maximum gain, which will then take a maximum of 8 m s. the receiver gain can also be selected manually by using the rxmgc mode. the settling target can be adjusted by 7 db from the nominal level of 500 mv peak, differential by means of register settings. note: when doing measurements with a single-tone rf signal, the amplitude at the rx outputs after settling the agc will be lower, at about 300 mv peak, differential .
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 7 6.7 agc handshake on the digital input pin agcreset, a 0-to-1 transition clears agcset output to logic 0 and starts the agc cycle. at the end of the agc settling, the agcset output is asserted to logic 1. the agcreset input can then be reset to logic 0. at any time in the receive mode the agc can be forced to the maximum gain by giving the agcreset signal as described, but by additionally re-setting it to logic 0 within 1 m s. the agcset indication is not given in this case and the receiver settling time is 3 m s. the channel filters will be set to have a lower cut-off of 1 mhz. for a timing diagram, please see the receiver parameters section. 6.8 rssi the receive signal strength indicator (rssi) is implemented as an error signal comparing the signal level at the rx output to the nominal value of 500 mv peak,differential . it has a 10 dbc to +10 dbc operational range relative to the nominal signal level. since the rssi acts on the modulated rf signal envelope that is extracted from the baseband i and q signals, it includes dc offsets, and will therefore show transient decaying errors when the ac coupling lower cut-off frequency is changed. the rssi signal reflects on a logarithmic scale the amplitude of the instantaneous modulated rf signal (envelope). the rssi signal is filtered by a low-pass filter with 0.5 mhz upper cut-off frequency. the sa2400a receiver is designed to give at least 10 dbc rssi at maximum gain, when there is no signal present, i.e., with only thermal noise. however, due to process spreads (e.g., gain, noise figure, iq low-pass filter bandwidth, etc.), the rssi may show higher than 10 dbc. in case a calibration is required for setting this noise power to 10 dbc, the agc's maximum gain (gmax) can be changed in the range of 85 to 54 db in steps of 1 db via register settings. the programmed value of maximum gain is never altered by the agc settling or by forcing the agc to maximum gain. only the rxmgc mode can set the agc gain to values higher than gmax. the rxmgc mode does not change the value of gmax. 6.9 receiver blocking immunity the receiver is designed to exceed the ieee802.11 specifications for the blocking and intermodulation. it can accept continuous or randomly pulsed interfering single- or multi-tone signals that are more than 35 db stronger than the wanted signal, and up to 10 dbm of interference level. the spurious i and q outputs are maintained to smaller than 20 dbc of the wanted signal level. 6.10 transmitter and iq upconverter the transmitter inputs are designed to be driven from a baseband ic in one of two modes: a) in analog mode, differential i and q inputs expect current signals driven by dacs in the baseband ic; or b) in digital mode, single-ended inputs expect two binary data streams. in this case, integrated firdacs provide additional filtering. the data streams are sampled with the reference clock. for timing specifications, please see the transmitter parameters section. the wide band iq upconverter includes spectral shaping reconstruction filters (4 th order low-pass butterworth with 9.75 mhz 3 db upper cut-off frequency). at +8 dbm maximum transmitter output level the out-of-band (fcc forbidden band) spurious signal power is less than 77 dbc (integrated over 1 mhz with a 100 khz resolution bandwidth) for the 11 msymbols/sec cck modulation (footnote 1 ). this implies that the spectral regrowth is dominated by any external pa that may be used to boost the transmission power level. in analog mode, it is assumed that the input baseband iq signals as delivered from the baseband ic are pulse shaped. by using the on-chip calibration loop, the transmitter carrier leakage can be reduced to levels far less than required by the standard. an rf power meter detects the lo level, converts it into a digital signal and a state machine determines the compensation values which are fed through a dac directly to the iq inputs. this mode is activated by setting the ic into the dcalib mode by means of 3-wire bus programming. this calibration is designed to compensate for any dc offsets delivered by the adcs on the baseband ic. the dcalib cannot be used when the ic is using the digital-input tx mode. the iq gain and phase imbalance, reconstruction filter roll-off and in-channel noise produce a modulation evm of less than 12% for 11 msymbols/sec qpsk. the transmitter has two switched outputs, one with 1.5 dbm output power and the other one with +8 dbm output power. the input pin tx_hi is used to select between the two rf output ports. the 8 dbm output port is differential and is designed to work seamlessly (no external filtering required) with the sa2411 power amplifier. upon entering the tx mode, the ramping up of the rf tx signal is delayed by an internal power ramping circuit. the ramping up time is fixed, while the delay prior to ramping up can be programmed by register settings. note: when switching out of the transmit mode (either into receive mode by transition on txrx pin, or into another mode by 3-wire programming), the reference clock input (pins xtal_1 and xtal_2) needs to be active since a digital timer is being used. 6.11 reference current and voltage outputs the ic provides a temperature-constant reference current of 1 ma or 300 m a (selectable), active in tx mode, as well as a 2.5 v reference voltage. 1. for a cck signal, the peak signal power is 21.7 db lower than the total power integrated over the 22 mhz band. the sa2400a gu arantees better than 56 dbc suppression of the second sidelobe (greater than 22 mhz frequency offset). consequently, the power level in the forbidden bands is at least 77 dbc below the transmitted integrated power.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 8 7. operating conditions table 3. absolute maximum ratings symbol parameter min max unit t stg storage temperature 55 +150 c v dd supply voltage 0.5 +3.85 v voltage applied to inputs 0.5 v dd +0.5 v short circuit duration, to gnd or v dd 1 second table 4. recommended operating conditions symbol parameter min nom max units t amb ambient operating temperature (note 1) 30 +85 c v dd supply voltage 2.85 3.3 3.6 v note: 1. when the digital input mode is used, the lower limit of the ambient operating temperature is higher than 30 c. preliminary characterization results suggest a limit of 20 c. this does not apply if the analog input mode is used. 8. operational modes and current consumption (see also table 18). table 5. operational modes and current consumption t amb = 25 c; v cc = 3.3 v. main mode duration current (ma) chip state main mode (register 0x04) other conditions description d u ration (max.) min typ max power-up sleep xo on, clock output on n/a 1.8 2.2 2.7 sleep sleep xo off note 1. n/a 0.05 tx hi tx/rx or fasttxrxmgc txrx = high; tx_hi = high synthesizer on. transmitter on with 8 dbm driver. maximum gain. n/a 120 143 170 tx lo tx/rx or fasttxrxmgc txrx = high; tx_hi = low synthesizer on. transmitter on with 1.5 dbm driver. maximum gain. n/a 81 95 105 rx tx/rx or rxmgc or fasttxrxmgc txrx = low synthesizer on. receiver on. receiver gain control by: ? tx/rx ? internal agc ? rxmgc ? 3-wire bus programming ? fasttxrxmgc ? fast 3-wire bus n/a 81 95 105 wait wait only synthesizer and xtal oscillator on n/a 27 31 34 fcalib fcalib calibrates cut-off frequency of tx and rx filters internally. automatic transition to sleep mode upon completion. 3 m s n/a dcalib dcalib maintain tx mode for 5 m s before calibration. quiescent iq input. analog mode used. calibration to reduce transmitter carrier leakage. automatic transition to sleep mode upon completion. 20 m s n/a vcocalib vcocalib calibrates internal vco. 2200 m s n/a reset reset resets ic into power-up state (sleep mode and all registers at default values) n/a n/a note: 1. all digital inputs connected to gnd or v dd .
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 9 8.1 reset shuts down all blocks except the 3-wire digital section, and programs internal registers to known default values that are described in section 13. this ensures that the sa2400a transmitter, receiver, synthesizer and other blocks enter a known state when made active. the sa2400a enters the sleep state automatically after the reset state. before entering either the txrx or rxmgc active states, the internal registers can be reprogrammed to change their values from the default values. a power-up of the digital supply also forces the sa2400a to the reset mode. 8.2 sleep all blocks (except the xtal osc) are off. the xtal osc can be separately shut down. note that the 3-wire bus will remain operational in all modes as long as the digital supply is on. the sa2400a retains programmed values of all active modes when it comes out of the sleep mode. this includes the synthesizer operation. programmed via 3-wire bus. 8.3 wait the pll is on. receiver and the transmitter are both off. this mode is useful for a quick turn-around to either txrx or rxmgc modes. transition to or from this mode is done via the 3-wire bus. 8.4 rxmgc only the pll and receiver are operating. the agc gain is manually set by the value of a register field. 8.5 txrx in this mode the logic level on the tx/rx input pin determines the operational mode: 1 = transmit, 0 = receive. this way, no 3-wire bus programming is necessary to switch between tx and tx, resulting in faster switching. when entering the receive mode (either via 3-wire programming to txrx mode with tx/rx pin at logic zero, or by a 1-to-0 transition of tx/rx pin when already in the txrx mode), the receiver is set to maximum gain. an agc cycle is initiated by a 0-to-1 change on the agc_reset digital input pin. at any time in the receive mode, the agc can be forced to the maximum gain setting by giving a 1 m s pulse on the agc_reset input while the tx/rx input is held at logic 0. 8.6 fasttxrxmgc it is similar to the rxmgc mode, except that the manual agc gain programming can be done faster, as described in section 14.5. 8.7 fcalib this mode needs to be programmed after power on in order to internally calibrate the cut-off frequency of the on-chip transmit and receive active filters. upon completion of the calibration, the ic will automatically switch to main mode = sleep. this calibration takes a maximum of 3 m s measured from the end of the programming sequence. the result of this calibration can be read out from register word 0x04. 8.8 dcalib if the analog tx inputs are used, this mode needs to be programmed at least once after power on in order to reduce the transmitter carrier leakage. this mode should be programmed after being in tx mode for at least 5 m s. upon completion of the calibration, the ic will automatically switch to main mode = sleep. this calibration takes a maximum of 20 m s measured from the end of the programming sequence. the result of this calibration can be read out from register 0x07. 8.9 vcocalib this mode needs to be programmed at least once after power on in order to calibrate the internal vco. upon completion of the calibration, the ic will automatically switch to main mode = sleep. this calibration takes a maximum of 2.2 ms from the end of the programming sequence. after this calibration, the synthesizer must be re-programmed by writing the register words 0x00 through 0x03. the result of this calibration can be read out from register 0x08.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 10 9. sa2400a receiver the baseband output signal extends from dc to 8 mhz, and the out-of-band frequency begins from 11 mhz. the modulated test signa l used is 11 msymbols/sec qpsk with raised cosine filtering (50% excess bandwidth for 11 msymbols/sec). the lo frequency is the same as t he receiver channel center frequency, as the if output is at 0 hz. table 6. sa2400a receiver properties t amb = 25 c; v cc = 3.3 v; f lo = 2.45 ghz. specification conditions min typ max units rf input frequency range typical 2.4 2.5 ghz s11 (rf input) incl balun+matching. 50 w unbalanced. note 3. lna in high gain (see reg. description 0x06) 10 db lna in low gain 7 db maximum rx voltage gain rf input to i or q outputs 90 93 db max rf input level including application, agctarget = +5. note 1. 10 dbm to maintain nominal iq output levels as defined below (anominal i and q output voltageo) 20 dbm iq output dc error (relative to signal, 5 m s after agc set) 80 dbm < p input < 20 dbm, 1 mhz sinewave output. note 3. 20 dbc agc settling time (indicated by agc_set digital output) initiated by agc_reset input. constant rf input within this settling time. begins after tx to rx switching time. measured from agc_reset 01 transition. agc delay registers (0x05) at default or smaller values. note 2. a) first instance 8 m s b) 2 nd or subsequent instances 11 m s agc max gain settling time agc forced to gmax by: a) tx to rx mode transition. (measured after 5 m s txrx settling time). 0 m s b) pulse on agc_reset pin (measured from end of programming) 3 m s note 2. agc max gain adjustment range note 2. 54 to 85, in steps of 1 db agc error (i, q signal levels) rf input between 75 to 20 dbm. agc_reset used. agc delay registers (0x05) at default values. a) random (varies each agc cycle) 3 3 db b) slow (varies with v cc , temperature). 1 1 db c) static (fixed, part to part) 1 1 db dc cancellation time ( ft agcreset) with constant rf input during this time. note 3. ( a f ter agcreset) a) dc offset < 50% of output signal level 8 m s b) dc offset <10% of output signal level 13 m s tx to rx switching time output signal within 1 db of final value, frequency error within 25 ppm of final value. note 3. 3 3.5 m s noise figure (i l b l t hi ) less than the piece-wise linear interpolation. note 3. (i nc l b a l un+matc hi ng ) p input = 85 dbm (lna in high gain mode) 7.5 9 db 75 dbm 7.5 9 db 60 dbm (lna in low gain mode) 24 25 db 45 dbm 24 25 db input ip3 (50 w source resistance) 2 interfering tones of power p interferer each, at 13 and 23 mhz offsets from lo. ip3 to be more than the piece-wise linear interpolation: p interferer = 39 dbm 5 1 dbm 1 db compression of wanted signal including matching, receiver at minimum gain. 10 0 dbm desens by jammer 45 dbm wanted signal at 1 mhz offset, +40 dbc jammer at 25 mhz offset. note 3. 1 db
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 11 specification units max typ min conditions lo leakage to antenna all gain modes. incl balun 75 57 dbm residual sideband rejection measured with single tone at 2 mhz offset from carrier. includes both iq gain and phase error. notes 3, 7. 22 29 db ripple band width of filter note 4. 5.6 6.3 7.0 mhz 3 db band width of filter indicative, not tested. note 4. 7 mhz in-band amplitude ripple dc to ripple band width edge. note 3. 0.6 db peak out-of-band attenuation relative to minimum in-band gain > 11 mhz 25 db > 22 mhz 55 db lower 3 db cut-off frequency of ac li cascade of two 1st order high-pass filters. coup li ng a) narrow band 10 khz b) intermediate band 100 khz c) wide band 1000 khz output load resistance pin to gnd, differential. note 5. 15 k w output load capacitance pin to gnd 6 pf nominal i & q output voltage differential at the load specified. note 6. 0.5 v peak maximum i & q output voltage saturated, differential 1.5 v peak common mode iq voltage programmable (see 0x04) mode 1 v cc /20.25 v cc /2 v cc /2+0.25 v mode 2 1.0 1.25 1.5 v 1 db compression level at output 1 mhz tone, differential. maximum gain. 1 v peak total harmonic distortion (measured at max and min gains) input 1 5 mhz signal, 1 v peak differential sinusoidal at output, output spurs measured differential up to 100 mhz. ratio of rms total spurious distortion to rms fundamental. receiver in minimum gain. note 3. 2 4 % receiver in maximum gain. note 3. 5 10 % phase imbalance signal tone input at 2 mhz offset from carrier. indicative, not tested. 4 deg i, /i to q, /q amplitude imbalance ratio of signal at i pin to /i pin; same for q and /q pins. 0.1 db rssi voltage in settled state (internal agc) corresponds to i, q output signal levels when agc_reset is used, with rf input between 10 and 80 dbm. 1 mhz tone, 0.5 v peak differential. acgtarget = 0 1.25 1.55 1.95 v rssi voltage difference 1 db change in input power compared to settled state 64.5 mv rssi minimum voltage signal power = 10 dbc 0.9 v rssi maximum output voltage signal power = +10 dbc 2.2 v rssi error 10 dbc < signal power < +10 dbc 1 db notes: 1. corresponds to 15 dbm input level at ic input, assuming typical 5 db loss from the antenna to the ic input. the agctarget re gister should be set to a+5o which causes the agc to settle to an output amplitude greater than the specified nominal value. a resisti ve divider network at the output can be used to adjust the actual iq output levels to the bb adc range. 2. guaranteed by design. 3. verified by bench characterization and found to have sufficient margin for production. 4. at power-up time, the filter bandwidth is undefined. it needs to be calibrated with the internal tuner (fcalib mode). 5. for unsymmetrical loading, attach the same load impedance to the unused pin; condition: for 80% of nominal output voltage swi ng. 6. nominal i/q output levels are understood as the levels the sa2400a will settle to after an agcreset action is performed with an rf input signal modulated by a barker sequence, and with agctarget = 0. 7. rsb = 20*log(sqrt([1+k 2 + 2kcos j ]/[1+k 2 2kcos j ])), where k = linear gain imbalance, and j = phase imbalance.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 12 9.1 agc handshake and timing rx turn-on regular settling set maxgain regular settling txrx agcreset agcset t h,agcreset t dsettle t drxon t reset t restart t r,agcreset sr02417 figure 3. agc handshake and timing. table 7. agc timing symbol parameter condition min typ max units agc logic level requirements v ih high-level logic input voltage 0.5 v dd v dd +0.3 v v il low-level logic input voltage 0.3 0.2 v dd v agcreset timing t r,agcreset input rise time 10 40 ns t h,agcreset input hold time to execute agc settling 5 8 m s ,g to set agc to max. gain 0.5 1 m s t restart time between agc cycles (note 1) 1 m s agcset timing t drxon settling time after switching to rx 5 m s t reset clearing time after agcreset 180 ns t dsettle agc settling time 11 m s notes: 1. in certain time interval further agcreset rising edges will not be detected. this applies for 4.3 m s < t restart < 4.8 m s.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 13 10. sa2400a transmitter the iq baseband input signal used is 11 msymbols/sec qpsk with pulse shaping and 44 mhz d/a sampling rate. the source evm is le ss than 3%. the lo frequency is the same as the transmitter channel center frequency, as the transmit if input is at 0 hz. table 8. sa2400a transmitter properties t amb = 25 c; v cc = 3.3 v. specification conditions min typ max units rf output frequency typical 2.4 2.5 ghz rf output power incl balun, output1, maximum 4.5 8.0 dbm for a cck modulated signal output2, maximum 5 1.5 dbm gain step size output1 and output2 1 db # gain steps output1 and output2 15 spectral mask (output1) n1 11 to + 11 mhz, 100 khz band 0 dbc note 1. 22 to 11 and 11 to 22 mhz, 100 khz band 40 36 dbc < 22, > 22 mhz, 100 khz band 60 56 dbc spectral mask (output2) 11 to + 11 mhz, 100 khz band 0 dbc note 1. 22 to 11 and 11 to 22 mhz, 100 khz band 30 dbc < 22, > 22 mhz, 100 khz band 50 dbc power ramping up time 10% to 90% ramp up. note 2. 0.5 m s power ramping up delay (note 3) from programming to transmit mode (txrx mode, or 0-to-1 change of tx/rx pin). note 2. 2 m s power ramping down note 2. a) 90% to 10% ramp down 0.5 m s b) 10% to carrier leakage level 0.5 m s carrier leakage analog input mode selected. no signal input, only quiescent current. a) uncalibrated 25 dbc b) calibrated 40 30 dbc digital input mode selected. 40 28 dbc carrier leakage adjustment adjustment range of input current offset 10 +10 m a residual sideband rejection includes both iq phase and gain imbalance 22 db error vector magnitude 11 msymbols/s qpsk. both rf outputs. measured with maximum gain. note 2. 12 14 % rx to tx switching time note 2. a) output power within 1 db of final value. includes 2.5 m s for power-up delay and ramping. 3 3.5 m s b) frequency step settles to within 25 ppm of final value 3 3.5 m s iq filter bandwidth upper 3 db cut off frequency, after calibration. note 2. 9.25 9.75 10.25 mhz in-band iq common mode rejection ratio 16 mhz common mode signal at 30 dbc relative to iq differential signal. measured at upconverted transmitter output. note 2. 30 db out-of-band iq common mode rejection ratio 22100 mhz common mode signal at 10 dbc relative to iq differential signal. measured at upconverted transmitter output relative to in-band 1 mhz tone. note 2. 40 db iq input signal current range into each arm of differential inputs that sink current to ground. analog input selected. note 4. 50 550 m a iq input quiescent current into each arm of differential inputs that sink current to ground. analog input selected. 300 m a resulting i/q bias voltage with 300 m a quiescent current into each arm of differential inputs. analog input selected. 0.6 0.7 0.8 v iq ac input impedance analog input selected. 320 w iq input voltage digital input selected logic low 0.2v dd v logic high 0.8v dd v
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 14 specification units max typ min conditions iq input timing digital input selected, sampling on falling edge, l i ref clk out set-up time 4 ns relative to ref_clk_out hold time 4 ns notes: 1. the 44 mhz common mode digital ground bounce on the i and q inputs is assumed to be less than 30 dbc relative to signal leve l. 2. verified by bench characterization and found to have sufficient margin for production. 3. the power ramping-up delay can be programmed to 2, 3, 4, 5 m s. see the 3-wire bus control register map. the default is 2 m s. 4. the differential input signal current is the difference between the i and /i (q and /q) instantaneous currents. the peak diff erential current is therefore (i max i min )/2 = 500 m a. 11. vco and synthesizer table 9 lists the synthesizer specifications. the synthesizer has the same specification as the sa8027 fractional pll main loop without the phi speed-up mode. the phase comparator frequency used is typically 4 mhz (in fractional mode). the charge pump current is internal ly programmed using the 3-wire bus (synthesizer register c). the recommended charge pump current is 480 m a. an external reference input of 44 mhz or 22 mhz is supported. table 9. synthesizer and vco specifications t amb = 25 c; v cc = +3 v parameter test conditions limits units parameter test conditions min typ max units vco vco output frequency range 2.4 2.5 ghz vco gain (k vco ) v tune = 1.2 v 70 85 100 mhz/v open loop vco phase noise note 1. 1/f 2 roll off region; 0.5 mhz offset 113 107 dbc/hz external vco input levels differential; when device configured for external vco 10 0 dbm main divider n divider range 512 65535 reference divider fixed reference input (xtal_1 and xtal_2) f 22 mhz frequency 44 mhz r divider range (non-fractional) sm = `000' 4 1023 reference input level xtal_1 input 350 1300 mv pp input parallel resistance (xtal_1, xtal_2) f = 44 mhz; indicative, not tested 10 k w input parallel capacitance (xtal_1, xtal_2) f = 44 mhz; indicative, not tested 1.5 pf phase detector phase detector frequency 4.0 mhz charge pump charge pump current accuracy v cp = 0.5 v cc 20 +20 % charge pump compliance voltage 0.6 v dd - 0.7 v output current variation vs. v cp (note 2) v cp in compliance range 5 +5 % charge pump sink to source current matching v cp = 0.5 v cc 10 +10 % charge pump aoffo current leakage v cp = 0.5 v cc 5 1 5 na notes: 1. this is measured at the output1 rf port with the sa2400a in transmit mode, with static dc offset signals to the transmitter i and q inputs. the phase detector and divide-by-n phase noise is such that when configured as a phase locked loop with a 30 khz loop band widt h, the phase noise at frequencies between 1 khz and 30 khz will be no worse than 80 dbc/hz. the total closed loop spur power within a 22 mhz band around the carrier is less than 30 dbc. 2. the relative output current variation is defined as: i zout i out 2 (i 2 i 1 ) i 2 i 1 with i 1 @ v 1 = 0.6 v, i 2 @ v 2 = v cc 0.7 v (see figure 4).
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 15 i 2 i 1 i 2 i 1 v 1 v 2 current v ph sr00602 i zout voltage figure 4. 12. functional description 12.1 main fractional-n divider the divider consists of a fully programmable bipolar prescaler followed by a cmos counter. total divide ratios range from 512 to 65535. at the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. also, the fractional accumulator is incremented by the value of nf. the accumulator works with modulo q set by fm (synthesizer register a). when the accumulator overflows, the overall division ratio n will be increased by 1 to n + 1, the average division ratio over q main divider cycles (either 5 or 8) will be nfrac n nf q the output of the main divider will be modulated with a fractional phase ripple. the phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. the reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance. 12.2 reference divider the reference divider consists of a divider with programmable values between 4 and 1023 followed by a 3-bit binary counter. the 3-bit sm register (see figure 5) determines which of the five output pulses are selected as the main phase detector input. sr02354 divide by r /2 /2 /2 /2 reference input sm=a000o sm=a001o sm=a010o sm=a011o sm=a100o to main phase detector figure 5. reference divider
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 16 12.3 phase detector (see figure 6) the reference and main divider outputs are connected to a phase/frequency detector that controls the charge pump. the pump current is set by the control bit cp (synthesizer register c). the dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by forcing the pumps on for a minimum time ( t ) at every cycle (backlash time) providing improved linearity. sr02355 r m p n ref divider main divider d q clk 1 r d r clk 1 m q n p t v cc i ph gnd ptype charge pump ntype charge pump r f ref f ref i ph t t f rf figure 6. phase detector structure with timing
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 17 12.4 main output charge pumps and fractional compensation currents (see figure 7) the main charge pumps on pin cp are driven by the main phase detector and the charge pump current value is determined by bit cp (synthesizer register c). the fractional compensation is derived from the contents of the fractional accumulator frd and by the program value of the fdac. the timing for the fractional compensation is derived from the main divider. the charge pumps will enter speed-up mode after sending a synthesizer register a word and stays active until a different word is sent. 12.5 principle of fractional compensation the fractional compensation is designed into the circuit as a means of reducing or eliminating fractional spurs that are caused by the fractional phase ripple of the main divider. if i comp is the compensation current and i pump is the pump current: i pump_total = i pump + i comp . the compensation is done by sourcing a small current, i comp , see figure 8, that is proportional to the fractional error phase. for proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the fractional charge pump ripple. the width of the fractional compensation pulse is fixed to 128 vco cycles, the amplitude is proportional to the fractional accumulator value and is adjusted by fdac values (bits fc70 in synthesizer b). the fractional compensation current is derived from the main charge pump in that it follows all the current scaling through programming or speed-up operation. for a given charge pump, i comp = (i pump / 128) * (fdac / 5*128) * frd frd is the fractional accumulator value. the target values for fdac are: 128 for fm = 1 (modulo 5) and 80 for fm = 0 (modulo 8). 12.6 lock detect the output lock maintains a logic `1' when main phase detector indicates a lock condition. the lock condition is defined as a phase difference of less than 1 period of the frequency at the input xtal_1, xtal_2. out of lock (logic `0') is indicated when the synthesizer is powered down. 12.7 power-down mode the power-on signal is defined by the bit on in synthesizer register b. if on = `1', the synthesizer section is powered on/off as defined by the chip mode (register 0x04). if on = `0', it is defined as inverted to the chip mode. when the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up. sr01416 ref. divider output r main divider output m detector output accumulator fractional compensation current output on pump n n n+1 n n+1 241 3 0 pulse width modulation pulse level modulation ma m a note: for a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the ch arge pump ripple output. figure 7. waveforms for nf = 2 modulo 5 fraction = 2 / 5 sr01800 f rf main divider fractional accumulator f ref i comp i pump loop filter & vco s figure 8. current injection concept
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 18 13. sa2400a other functionality table 10 specifies functionality not described elsewhere in this document. table 10. sa2400a other functionality t amb = 25 c; v cc = 3.3 v parameter test conditions limits units parameter test conditions min typ max units reference voltage output, pin v_2p5 i load < 2 ma, c load < 10 pf; switched on via register 0x04 bit 14 = `1' 2.25 2.5 2.75 v reference current output, pin idcout register 0x04 bit 12 = `1'; asink currento measured from supply to ic pin 0.25 0.3 0.35 ma register 0x04 bit 13 = `1'; asource currento measured from ic pin to ground 0.85 1.0 1.15 ma 14. 3-wire bus/logic control a simple 3-line bi-directional serial bus is used to program the circuit. the 3 lines are sdata, sclk and sen. the sdata line is bi-directional while the sclk and sen signals are always supplied externally: ? the pin sen is an aenableo signal. it is level sensitive: if sen is of low value, the 3-wire bus interface on the sa2400a is enabled. this means that each rising edge on the sclk pin (see below) will be taken as a shift cycle, and address/data bits are expected on sdata (see below). if sen is high, the 3-wire bus interface is disabled. no register settings will change regardless of activity on sclk and sdata. ? the pin sclk is the ashift clocko input. if the 3-wire bus is enabled, address or data bits will be clocked in from the sdata pin with rising edges of sclk. in output mode, sdata bits are set on the falling edge of sclk in order to be sampled on the rising edge by the controller. ? the pin sdata is the bi-directional adatao pin. it is internally configured as ainputo or aoutputo depending on the operation (write or read). each operation consists of 32 bits. out of these, the first 7 bits form an address word, followed by a read/write indicator bit. the following 24 bits are the data word corresponding to the chosen address. the 3-wire bus interface contains an internal counter (state machine) which determines beginning and end of address and data word, the awriteo pulse to the internal registers, and the direction of the bi-directional sdata pin. consequently, with the 32 nd rising sclk edge of a write cycle, the current data word is stored in the internal register of the programmed address. following sclk edges will be taken as the beginning of the following cycle. no programming on sen is needed to separate cycles. if the sen signal is switched to high (i.e., disable) at any time, the current cycle will be disregarded. any bits that have been shifted in so far via sdata will be disregarded. the internal counter is reset to zero. 14.1 description of write cycle 1. (start) sen is low or is changed to low, i.e., 3-wire interface is enabled. 2. (sclk edge 1 through 7) 7 address bits are clocked in, lsb first. the bit values on sdata are taken over with rising edges on sclk. 3. (sclk edge 8) the read/write bit is clocked in with the rising edge of sclk. `1' = write, `0' = read. 4. (sclk edges 9 through 32) 24 data bits are clocked in, lsb first, with rising edges of sclk. with the 32 nd rising edge of sclk, the whole data word is stored in the internal register according to the selected address. 1234567891011 321 a0 a1 a2 a3 a4 a5 a6 r/w d0 d1 d2 d23 t on t setup t hold t cyc t r t f sclk sen sdata sr02288 figure 9. write cycle timing diagram of the 3-wire bus
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 19 14.2 description of read cycle 1. (start) sen is low or is changed to low, i.e., 3-wire interface is enabled. 2. (sclk edge 1 through 7) 7 address bits are clocked in, lsb first. the bit values on sdata are taken over with rising edges on sclk. 3. (sclk edge 8) the read/write bit is clocked in with the rising edge of sclk. `1' = write, `0' = read. 4. (sclk edges 9 through 32) 24 data bits are clocked out, lsb first. the bits will be available on the sdata pin with the falling edges of sclk (so bits can be accepted by the baseband ic with the following rising edge). 1234567891011 321 a0 a1 a2 a3 a4 a5 a6 r/w d0 d1 d2 d23 t on t setup t hold t cyc t r t f sclk sen sdata sr02289 t dout figure 10. read cycle timing diagram of the 3-wire bus the fully static cmos design uses virtually no current when the bus is inactive. it can always capture new data even during pow er-down. the data remains latched during power-down (sleep mode). 14.3 3-wire bus/logic control ac characteristics table 11. 3-wire bus/logic control ac characteristics symbol parameter test conditions limits units symbol parameter test conditions min typ max units serial bus logic level requirements v ih high logic input voltage 0.5 v dd v dd + 0.3 v v il low logic input voltage 0.3 0.2 v dd v serial programming clock, sclk t r input rise time 10 40 ns t f input fall time 10 40 ns t cyc clock period 22 100 ns enable programming, sen t on delay to rising clock edge 10 ns data programming, sdata t setup input data to clock set-up time 10 ns t hold input data to clock hold time 10 ns t dout output data to clock delay time ( falling edge) 10 ns
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 20 14.4 3-wire bus control register map 14.4.1 data format table 12. format of programmed data last in (msb) first in (lsb) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 table 13. overview address description 00 synthesizer: main divider settings write only 01 synthesizer: reference divider and fractional compensation write only 02 synthesizer: charge pump current and additional division write only 03 synthesizer: test modes write only 04 main operation modes, filter tuner, other controls 05 rx agc adjustment settings 06 manual receiver control settings 07 transmitter settings 08 vco settings (only bits 0 through 9) notes: 1. the synthesizer registers (addresses 00 to 03) cannot be read. 2. after programming register 0x01 it is necessary to also program register 0x00 to load the content of fc[7:0] into the interna l working register. 3. after programming register 0x00 it is necessary to program some other register (e.g., 0x04) to avoid keeping the charge pump current setting in php-speedup mode. 4. after running the vcocalib mode, it is necessary to re-program registers 0x00 through 0x03. table 14. address 00: synthesizer register a note: bits 22, 23 not used. main divider register bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fm nf[2:0] n[15:0] unused default 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 bit description fm fractional modulus select. 0>/8; 1>/5; default: 0 nf[2:0] fractional increment value (0 to 7); default: 4 n[15:0] main divider division ration (512 to 65535); default: 615 table 15. address 01 : synthesizer register b note: bits 22, 23 not used. bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r[9:0] l on fc[7:0] default 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 1 0 1 0 0 0 0 bit description r[9:0] reference divider ratio (4 to 1023); default: 11 l[1:0] lock detect mode 00> inactive 01> inactive 10>lock detect normal mode 11>inactive on power on/off 1: as defined by chip mode (register 0x04) 0: inverted chip mode control fc[7:0] fractional compensation charge pump current dac (0 to 255); default: 80
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 21 table 16. address 02: synthesizer register c note: bits 22, 23 not used. bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name unused cp[1:0] sm[2:0] `0' unused default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 bit description cp[1:0] charge pump current setting sm[2:0] comparison divider select adds an extra divider at the end of the reference divider: extra division ratio = 2^sm (sm = 0 to 4) cp[1:0] php php-speedup 00 480 m a 2.4 ma 01 160 m a 800 m a 10 480 m a 2.4 ma 11 160 m a 800 m a php-speedup is activated when the speed-up bit is 1 (t spu in synthesizer register d). php-speedup is also entered after sending a synthesizer register a word and stays active until a different word is sent. to prevent frequency deviations when leaving the speedup mode when programming new words, it is recommended to keep the speedup mode always disabled by setting the tphpsu (0x03, bit 16) to `1' . note: the only recommended charge pump current setting mode is cp[1:0] = 10, php-speedup not activated. table 17. address 03: synthesizer register d note: bits 22, 23 not used. bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name `00000' t phpsu t spu `000000000000' unused default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit description t phpsu 1 > disable php speedup pump, overrides function of t spu t spu 1 > speedup on 0 > speedup off
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 22 table 18. address 04: main chip operation modes, filter tuner, other controls bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name `0000' adc fterr filttune v2p5 i1m i0p3 n.u. in22 clk xo digin rxlv veo vei chip mode default 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 bit # name description 03 chip mode main mode of operation. coding according to following table: bit3 bit2 bit1 bit0 mode 0 0 0 0 sleep 0 0 0 1 tx/rx 0 0 1 0 wait 0 0 1 1 rxmgc 0 1 0 0 fcalib 0 1 0 1 dcalib 0 1 1 0 fasttxrxmgc 0 1 1 1 reset 1 0 0 0 vcocalib notes on modes: ? all calibration modes (*calib) require the crystal oscillator to be on (bit xo = 1). ? dcalib (tx lo leakage calibration) requires being in tx mode for 5 m s before calibration. 4 vei use external vco input (vcoextin) 5 veo make internal vco available at vco pads (vcoextout) 6 rxlv rx output common mode voltage: 0v dd /2, 11.25 v 7 digin use digital tx inputs (firdac) 8 xo xtal oscillator on 9 clk reference clock output on 10 in22 xtal input frequency: 044 mhz, 122 mhz 11 not used 12 i0p3 external reference current (pad idcout): 0.3 ma to ground 13 i1m external reference current (pad idcout): 1.0 ma from supply 14 v2p5 external reference voltage (pad v2p5) on 1517 filttune rx and tx filter tuning bits: write: (with test mode only), these bits set tuning value read: (in normal mode) tuner setting can be read out here 18 fterr filter tuner error (read only): result is 1 when tuner exceeded range 19 adc `1': in rx mode, the rssi-adc is always on. `0': the rssi-adc is only on during agc operation. table 19. address 05: agc adjustment settings bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx agc target rx agc gmax agc_bbdel/adcval agc_lnadel/sample2 agc_rxondel/sample1 default (0) val(000) 79 db 11001 7(1.3 m s) 00111 15(2.7 m s) 01111 27(4.9 m s) 11011 bit # name description 04 agc_rxondel/s1 write: programmable delay for agc algorithm: rx turn-on to agcset. in units of 182 ns (5.5 mhz) read: 1 st sample of rssi in agc cycle 59 agc_lnadel/s2 write: programmable delay for agc algorithm: settling time after lna gain switching. in units of 182 ns (5.5 mhz) read: 2 nd sample of rssi in agc cycle 1014 agc_bbdel/adcval write: programmable delay for agc algorithm: settling time after baseband gain switching. in units of 182 ns (5.5 mhz) read: output of rssi/txpeak detector adc in 5-bit gray code 1519 agc gmax rx agc gain limit (54 db + programmed value) (valid: 54 through 85) 2023 agc target adjustment value to agc settling target, range 7 db 7 db (sign plus three bits)
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 23 table 20. address 06: manual receiver control settings bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ahsn osq rxosqval osi rxosival ten corner f receiver gain default 0 0 (0) val (000) 0 (0) val (000) 1 0 0 1 1 1 1 1 1 1 1 1 1 bit # name description 09 receiver gain write: in rxmgc mode, this sets the receiver gain. read: in other modes, the agc controlled gain is available for readout here. bit positions: 0plus1db; 1vga2db; 2vga4db; 3vga8db; 4vga16db; 5vga10db; 6filter6db2; 7filter10db; 8filter6db1; 9lna16db 1011 corner freq. dc offset cancellation cornerpoint select. write: in rxmgc mode, this sets the cornerpoint. read: in other modes, the cornerpoint as controlled by the agc is available for readout here. code: 0010 khz, 01100 khz, 101 mhz, 1110 mhz 12 ten use 10 mhz offset cancellation cornerpoint for brief period after each gain change 1322 rx offset i,q receiver output driver manual offset adjustment. code: {rxosxon,rxosxval} = `0xxxx' offset = 0; {rxosxon,rxosxval} = `10000' offset = 8 mv; {rxosxon,rxosxval} = `11000' offset = 8 mv; {rxosxon,rxosxval} = `10001' offset = 16 mv etc. 1316 rxosival rx offset correction, i channel, value (sign plus three bits) 17 rxosion rx offset correction, i channel, on 1821 rxosqval rx offset correction, q channel, value (sign plus three bits) 22 rxosqon rx offset correction, q channel, on 23 ahsn agc with high signal-to-noise (switch lna at step 52 instead of step 60). recommended to set to `1'. table 21. address 07: transmitter settings bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name `0000' osq txosqval osi txosival txramp tx gain hi tx gain low default 0 0 0 0 0 (0) val (000) 0 (0) val (000) 0 0 0 db (0000) 15 db (1111) bit # name description 03 tx gain low transmitter gain settings for txlo output 47 tx gain hi transmitter gain settings for txhi output 89 txramp tx ramp-up delay programming: 001 m s, 012 m s, 103 m s, 114 m s. ramp-up time always 1 m s. 1019 tx offset i, q tx carrier leakage calibration: write: with test mode, these bits set the offset. read: in normal mode, automatically controlled settings can be read out here (sign plus three bits). code: {txosxon,txosxval} = `0xxxx' offset = 0; {txosxon,txosxval} = `10000' offset = 2.5 m a; {txosxon,txosxval} = `11000' offset = 2.5 m a; {txosxon,txosxval} = `10001' offset = 5.0 m a etc. 1013 txosival tx offset correction, i channel, value (sign plus three bits) 14 txosion tx offset correction, i channel on 1518 txsoqval tx offset correction, q channel, value (sign plus three bits) 19 txosqon tx offset correction, q channel on table 22. address 08: vco settings bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name these bits do not exist on ic not used `0' `0' vcerr vcoband default x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 bit # name description 03 vcoband vco band. write: with test mode, these bits set the vco band. read: in normal mode, the result ot the calibration (vcocal) can be read out here (0000 = highest frequencies). 4 vcerr vco calibration error flag (no band with low enough frequency could be found).
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 24 14.4.2 programming example program synthesizer for 2.412 ghz band ? input xtal is 44 mhz, comparison frequency f comp = 4 mhz ? reference division ratio r = 11 ? target frequency is 2412 mhz, f comp = 4 mhz ? main divider ratio n = 603 (no fractional n) write this word to register 00: 00 0 000 0000001001011011 00 (note two leading zeros unused bits 22, 23) write this word to register 01: 00 0000001011 00 1 0 xxxxxxxx (x = no significance) program synthesizer for 2.462 ghz band ? input xtal is 44 mhz, comparison frequency f comp = 4 mhz ? reference division ratio r = 11 ? target frequency is 2462 mhz, f comp = 4 mhz ? main divider ratio n = 615.5 (fractional 4/8) write this word to register 00: 00 0 100 0000001001100111 00 write this word to register 01: 00 0000001011 00 1 0 01010000 fractional compensation setting should be set in the application (depends on the loop parameters) with the help of the sa8027 application note. the nominal value is fc = 640 / fm (fm = modulus, see address 00). 14.5 fast serial interface for receiveragc programming when the chip is in mode afasttxrxmgco the internal agc block is disabled. instead, the 10 bits controlling the receiver gain and the two bits controlling the dc offset cancellation corner frequency can be programmed directly via a dedicated second serial interface. this interface is active when in fasttxrxmgc mode and when sen=high. (sen acts as a switch between the regular serial interface and the dedicated bus). 14.5.1 description of afast programmingo cycle 1. set the chip to fasttxrxmgc mode by programming register 4 with the correct value. 2. set the sen pin to high. 3. with each rising edge on pin sclk, a new data bit is expected at pin agcreset. no address is needed. the sequence of the bits is the same as described for register 6, bits 011. the programming order is lsb first. 4. with the 12 th rising edge on sclk, an internal counter will automatically parallel-load the shifted-in data bits into an internal register. the bits will immediately effect the receiver settings. 5. the regular 3-wire bus is still accessible and can be programmed when sen is low. clock activity on sclk will not affect receiver gain settings when sen is low. 1231321234511121 a0 a1 d23 d23 xx t on t setup t hold t cyc t r t f sclk sen sdata sr02311 a0 d0 d1 d2 d3 d4 d10 d11 xx 3wire bus programming afast buso programming agcreset figure 11. afast programmingo cycle timing diagram 14.6 fast serial interface ac characteristics parameter test conditions limits units symbol parameter test conditions min typ max units serial bus logic level requirements v ih high logic input voltage 0.5 v dd v dd + 0.3 v v il low logic input voltage 0.3 0.2 v dd v serial programming clock, sclk t r input rise time 10 40 ns t f input fall time 10 40 ns t cyc clock period 22 100 ns enable programming, sen t on delay to rising clock edge 10 ns data programming, agcreset t setup input data to clock set-up time 10 ns t hold input data to clock hold time 10 ns
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 25 15. performance curves sr02418 temperature ( c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 40 15 10 35 60 85 time ( s) m freq. ( m s) p out ( m s) figure 12. tx to rx switching time versus temperature (v dd = 3.3 v) sr02419 supply voltage, v dd (v) time ( s) m 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.7 3.0 3.3 3.6 freq. ( m s) p out ( m s) figure 13. tx to rx switching time versus supply voltage (t amb = 25 c) sr02427 input power (dbm) 0 5 10 15 20 25 30 85 75 65 55 45 noise figure (db) 2.7v 2.85v 3v 3.3v 3.6v figure 14. noise figure versus input power sr02420 temperature ( c) 27.5 28.0 28.5 29.0 29.5 30.0 30.5 40 15 10 35 60 85 side band rejection (db) figure 15. rx residual sideband suppression versus temperature (v dd = 3.3 v) sr02821 supply voltage, v dd (v) side band rejection (db) 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 2.7 3.0 3.3 3.6 figure 16. rx residual sideband suppression versus supply voltage (t amb = 25 c) sr02822 frequency (hz) power (dbm) 60 50 40 30 20 10 0 9.50e+07 9.70e+07 9.90e+07 1.01e+08 1.03e+08 1.05e+08 figure 17. spectrum of rx sideband rejection at 4 mhz offset
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 26 sr02460 figure 18. tx ramp-up (1 m s/div). sr02461 5 10 15 20 25 85 80 75 70 65 60 55 50 45 40 pin (dbm) nf (db) low high figure 19. noise figure vs. input power for two lna switching modes. sr02423 temperature ( c) 0 2 4 6 8 10 12 40 15 10 35 60 85 error vector magnitude (%) figure 20. transmitter error vector magnitude (evm) versus temperature (v dd = 3.3 v). sr02824 supply voltage, v dd (v) error vector magnitude (%) 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 2.7 3.0 3.3 3.6 figure 21. transmitter error vector magnitude (evm) versus supply voltage (t amb = 25 c). sr02425 temperature ( c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 40 15 10 35 60 85 time ( s) m freq. ( m s) p out ( m s) figure 22. rx to tx switching time versus temperature (v dd = 3.3 v). sr02426 supply voltage, v dd (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.7 3.0 3.3 3.6 time ( s) m freq. ( m s) p out ( m s) figure 23. rx to tx switching time versus supply voltage (t amb = 25 c).
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 27 sr02459 figure 24. tx constellation and evm.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 28 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 1.00 0.00 1.00 2.00 3.00 4.00 5.00 6.00 sr02445 temperature ( c) mean ( m a) figure 25. total sleep i cc . 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02446 temperature ( c) 108.00 112.00 116.00 120.00 124.00 mean (mhz) figure 26. vco 0011 bandwidth. 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02447 mean (mhz) temperature ( c) 2364.00 2392.00 2420.00 2448.00 figure 27. vco 0111 f1. 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02448 mean (ma) temperature ( c) 78.00 87.00 96.00 105.00 figure 28. total tx low i cc .
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 29 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02449 mean (dbm) temperature ( c) 10.00 5.00 0.00 figure 29. output power tx low, g = 1111. 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02450 mean (ma) temperature ( c) 120.00 130.00 140.00 150.00 160.00 figure 30. total tx high i cc . 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02451 mean (dbm) temperature ( c) 0.00 5.00 10.00 figure 31. output power tx high, g = 1111. 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02452 mean (dbc/hz) temperature ( c) 114.00 112.00 110.00 108.00 figure 32. pll phase noise @ 500 khz.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 30 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02453 mean (dbc) temperature ( c) 62.00 55.00 48.00 41.00 34.00 figure 33. tx high spectral mask, adjacent channel. 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02454 mean (dbc) temperature ( c) 60.00 50.00 40.00 30.00 figure 34. tx low spectral mask, adjacent channel. 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02455 mean (ma) temperature ( c) 80.00 86.00 92.00 98.00 104.00 figure 35. total rx i cc . 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02456 mean (db) temperature ( c) 84.00 86.00 88.00 90.00 92.00 94.00 figure 36. rxmgc i max gain.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 31 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02457 mean (db) temperature ( c) 84.00 86.00 88.00 90.00 92.00 94.00 figure 37. rxmgc q max gain. 2.70 v 2.85 v 3.00 v 3.30 v 3.60 v 30 0 25 70 85 sr02458 mean (mhz) temperature ( c) 6.25 6.40 6.55 6.70 6.85 figure 38. rx filter ripple bandwidth.
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 32 lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 33 revision history rev date description _1 20021104 product data; initial version. engineering change notice 8532320 28727 (date: 20020809).
philips semiconductors product data sa2400a single chip transceiver for 2.45 ghz ism band 2002 nov 04 34 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2002 all rights reserved. printed in u.s.a. date of release: 11-02 document order number: 9397 750 09632

data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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